專利名稱：Logic modification synthesis

發(fā)明人：Eli Arbel,David Geiger,Victor Kravets,Smita

Krishnaswamy,Ruchir Puri,Haoxing Ren

申請?zhí)枺篣S12862838申請日：20100825公開號：US08365114B2公開日：20130129

專利附圖：

摘要：Two circuits, an original and a modified, are being recognized, with the originalcircuit having a first logic and the modified circuit having a second logic. The second logiccontains at least one desired logic change relative to the first logic. An equivalence line is

detected in the original circuit such that the first and second logic are equivalent fromthe circuit inputs to the equivalence line. At least one point of change is located amongstthe logic gates that are neighboring the equivalence line. The points of change areaccepted as verified if an observability condition is fulfilled. The observability condition ischecked within a Boolean Satisfiability (SAT) formulation. Substitute logic for the verifiedpoints of change is derived using SAT and Boolean equation solving techniques, in suchmanner that the first logic becomes equivalent to the second logic.

申請人：Eli Arbel,David Geiger,Victor Kravets,Smita Krishnaswamy,Ruchir Puri,HaoxingRen

地址：Nesher IL,Peekskill NY US,New York NY US,New York NY US,Baldwin Place NYUS,Austin TX US

國籍：IL,US,US,US,US,US

代理人：George Sai-Halasz,Preston J. Young

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