專利名稱：3D integrated circuit structure and method

for detecting chip mis-alignement

發(fā)明人：Huilong Zhu申請?zhí)枺篣S13203030申請日：20110223公開號：US083753B2公開日：20130115

專利附圖：

摘要：The present application discloses a 3D integrated circuit structure and amethod for detecting whether there is misalignment between chip structures. The circuitstructure comprises a first chip structure which comprises a first semiconductor

substrate, a first insulating layer, and a first detection structure; the first detectionstructure comprises detection bodies positioned on two sides of the first insulating layer,the detection body comprising a first conductor, at least two second conductors, and atleast one third conductors; wherein the first conductor is located on a side of the firstinsulating layer and connected with ends of the second conductors; the third conductorsare formed between the second conductors and insulated from the second conductors,and the first ends of the third conductors away from the first conductor are step-wise;wherein vertical distances between the third conductors and the second conductors areequal, and in the direction of the length of the third conductors, the distances betweenthe projections of the ends of the third conductors away from the first conductor whichare corresponding to each other and located on the detection bodies on the two sidesare substantially the same. The present invention is suitable for optimizing the alignmentbetween the chip structures in manufacture of integrated circuits.

申請人：Huilong Zhu

地址：Poughkeepsie NY US

國籍：US

代理機構(gòu)：Troutman Sanders LLP

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